معرفی آی سی های سینتی سایزر

[jfrras]

سلام دوستان
در این بخش اطلاعاتی آی سی های سینتی سایزر یا اصطلاحا قفل کننده فاز(فرکانس) قرار میگیرد.

شما میتونید با این آی سی ها ثبات فرکانسی فوق العاده به میکروفن بی سیم و فرستنده اف ام و گیرنده اف ام بدید.



در این نمونه که در تلفنهای بیسیم و مرکز سانترال هستند از ای سی MC145158 استفاده شده.
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[h=1]Using the MC145158 PLL Frequency Synthesizer[/h]

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Overview

The Motorola MC145158 is a dual-modulus, serial-input PLL frequency synthesizer which is commonly used in older Motorola cellular phones. Refer to the MC145158's datasheet for the nitty-gritty technical details. The MC145158 is no longer manufactured, but it does pop up from time-to-time in surplus electronic stores. Digi-Key used to carry it, part number MC145158DW2-ND. The Fujitsu equivalent is the MB87001A, which is very common in old Japanese-manufactured (Uniden, Toshiba, etc.) cellular phones. The programming of the MB87001A is the same as the MC145158, but the technical specs to the MB87001A are slightly different.
The maximum input frequency for the MC145158 is only around 20 MHz when run at +9 VDC. It drops to around 15 MHz at +5 VDC. The R-Counter reference frequency divider range is between 3 and 16,383. The N-Counter can be between 3 and 1,023. The A-Counter dual-modulus range is between 0 and 127. When using an external dual-modulus prescaler set to /64 (divide-by-64), such as a Motorola MC12022 or Fujitsu MB501, don't exceed a value of 63 for the A-Counter.
The MC145158 is designed to be programmed via a microcontroller using a standard serial-input data stream. The MC145158 has pins for the shift clock (CLK, pin 9), serial data input (DATA, pin 10), and latch enable (ENB, pin 11). These three lines control how and when the PLL is programmed. Once programmed, all the counter's values will remain programmed until power is removed from the circuit. Also, the counters must be programmed Most Significant Bit (MSB) first.

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From the MC145158's datasheet:
CLK, DATA
Shift Clock, Serial Data Inputs (Pins 9, 10)
Each low-to-high transition of the CLK shifts one bit of data into the on-chip shift registers. The last data bit entered determines which counter storage latch is activated; a logic 1 selects the reference counter latch and a logic 0 selects the /A, /N counter latch. The data entry format is as follows:

END
Latch Enable Input (Pin 11)
A logic high on this pin latches the data from the shift register into the reference divider or /N, /A latches depending on the control bit. The reference divider latches are activated if the control bit is at a logic high and the /N, /A latches are activated if the control bit is at a logic low. A logic low on this pin allows the user to change the data in the shift registers without affecting the counters. ENB is normally low and is pulsed high to transfer data to the latches.
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What this means, in English, is that to program the counter data into the MC145158, you need to set the voltage on the DATA pin to +5 volts for a logic 1, and 0 volts (ground) for a logic 0. You'd then raise the CLK pin to +5 volts, from it's initial value of 0, then quickly bring it back to 0 volts. Do this 15 times to load the R-Counter value (14 bits, plus one control bit). When finished, raise the ENB pin to +5 volts, from it's initial value of 0, then quickly bring it back to 0 volts. The data is permanently latched into the counters. To load the /N and /A counters, do the same again, but you'll need to load 18 bits (17 bits, plus one control bit).

MC145158-to-PIC16F84 pin connections for the example MC145158 loader code which will be used:

MC145158-to-PIC16F84 Connections
MC145158 Line	MC145158 Pin #	16F84 Port	16F84 Pin #
DATA	10	B0	6
CLK	9	B1	7
ENB	11	B2	8

The following is an easy-to-follow example using PICBasic and a Microchip PIC16F84. The R-Counter will be programmed with a value of 2600, the N-Counter with a value of 133, and the N-Counter with a value of 7:

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' Load /R counter with a value of 2600, MSB first Gosub zero ' 8192 Gosub zero ' 4096 Gosub one ' 2048 Gosub zero ' 1024 Gosub one ' 512 Gosub zero ' 256 Gosub zero ' 128 Gosub zero ' 64 Gosub one ' 32 Gosub zero ' 16 Gosub one ' 8 Gosub zero ' 4 Gosub zero ' 2 Gosub zero ' 1 Gosub one ' CONTROL, R = 1 Gosub enable ' ENABLE ' Load /N counter with a value of 133, MSB first Gosub zero ' 512 Gosub zero ' 256 Gosub one ' 128 Gosub zero ' 64 Gosub zero ' 32 Gosub zero ' 16 Gosub zero ' 8 Gosub one ' 4 Gosub zero ' 2 Gosub one ' 1 ' Load /A counter with a value of 7, MSB first Gosub zero ' 64 Gosub zero ' 32 Gosub zero ' 16 Gosub zero ' 8 Gosub one ' 4 Gosub one ' 2 Gosub one ' 1 Gosub zero ' CONTROL, N & A = 0 Gosub enable ' ENABLE End zero: Low 0 ' Load 0 on pin 6 (Port B0 - DATA) High 1 ' Bring pin 7 high (Port B1 - CLK) Low 1 ' Then back low Return one: High 0 ' Load 1 on pin 6 (Port B0 - DATA) High 1 ' Bring pin 7 high (Port B1 - CLK) Low 1 ' Then back low Return enable: High 2 ' Bring pin 8 high (Port B2 - ENB) Low 2 ' Then back low Return

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Here is an example of PICBasic code which uses the SHIFTOUT command. It's operation will be much faster, and will not use as much memory in the PIC16F84. The R-Counter will be programmed with a value of 2600, the N-Counter with a value of 133, and the N-Counter with a value of 7:

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RVAL VAR WORD NVAL VAR WORD AVAL VAR BYTE RVAL = 2600 NVAL = 133 AVAL = 7 ' SHIFTOUT data, clock, mode, [var\bits] ' SHIFTOUT 0,1,1,[RVAL\14] ' Load /R counter with a value of RVAL (14 bits), MSB first SHIFTOUT 0,1,1,[1\1] ' CONTROL, R = 1 High 2 ' Bring pin 8 high (Port B2 - ENB) Low 2 ' Then back low SHIFTOUT 0,1,1,[NVAL\10] ' Load /N counter with a value of NVAL (10 bits), MSB first SHIFTOUT 0,1,1,[AVAL\7] ' Load /A counter with a value of AVAL (7 bits), MSB first SHIFTOUT 0,1,1,[0\1] ' CONTROL, N & A = 0 High 2 ' ENB Low 2 End

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Here is some example PICBasic code which will continuously increment the /N and /A counters on a MC145158. It was originally designed to be a synthesized cellular phone jammer, but the combination of PICBasic and the PIC16F84 proved to be much too slow. The reference oscillator for this code was 15.36 MHz, with a R-Counter of 512. This gives a reference frequency of 30 kHz, standard for cellular phone applications. The MC145158 used an external MC12022B dual-modulus prescaler, set at /64. The rest of the PLL math looks like:

Reference Oscillator : 15.36 MHz Reference Frequency : 30,000 Hz /R Counter Value : 512 /N Counter Value : 452 to 465 /A Counter Value : 0 to 63 Target Frequencies : 867.84 MHz to 894.69 MHz Example (452 * 64) + 0 = 28,928 28,928 * 30,000 = 867.84 MHz ... (465 * 64) + 63 = 29,823 29,823 + 30,000 = 894.69 MHz

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DEFINE SHIFT_PAUSEUS 1 NVAL VAR WORD AVAL VAR BYTE IVAL VAR BYTE SHIFTOUT 0,1,1,[512\14] ' Load /R counter with a value of 512 (14 bits), MSB first SHIFTOUT 0,1,1,[1\1] ' CONTROL, R = 1 High 2 ' ENB Low 2 ' Load /N counter with a value of NVAL (10 bits), MSB first ' Load /A counter with a value of AVAL (7 bits), MSB first ' CONTROL, N & A = 0 ' Loop 50 times For IVAL = 0 to 50 For NVAL = 452 to 465 For AVAL = 0 to 63 SHIFTOUT 0,1,1,[NVAL\10] ' /N Counter Shiftout 0,1,1,[AVAL\7] ' /A Counter Shiftout 0,1,1,[0\1] ' CONTROL High 2 ' ENB Low 2 Next AVAL Next NVAL Next IVAL End

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Pictures

Example of the old Motorola cellular phones which use a MC145158 PLL frequency synthesizer. The "brick" phone on the left is probably the most famous. Its PC board containing the MC145158 is shown next to it. The other PC boards on the right are from old Motorola TeleTacs.

Close up picture of the PC boards.

The 16-pin IC on the left is the MC145158 with Motorola "in-house" numbers printed on it.

Close up picture of a properly labeled MC145158.

I'm pretty sure that old Motorola bag phones used the MC145158.

It's underneath a RF shield. IMI was a company that often sold an equivalent to the Motorola PLL ICs. This could make turning old bag phones into 900 MHz amateur radio transceivers a possibility...

Experimental VCO/PLL board which was used for this article. The PIC16F84 went in the open socket on top. The silver box along the bottom is the 15.36 MHz reference clock oscillator. The VCO is a Z-Communications V580MC05.


Example of a Fujitsu MB87001A synthesizer and Motorola MC12022B prescaler as used in the PLL/VCO modules which are found in old Uniden cellular phones. Scarf these up!
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امیدوارم مورد توجه قرار گرفته باشه.
موفق باشید

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[jfrras]

سلام
دوستان عزیز اصول کار مدار سینتی سایزر رو ببینید . اصول کارشون تقریبا همشون یکی است.
آشنایی با آی سی سینتی سایزر mc145152

PHASE LOCKED LOOP - IN PLL FREQUENCY SYNTHESIZERThe PLL is a control circuit with feedback (feedback) phase-sensitive or frequency.
It consists of 3 basic parts: a phase detector, a low pass filter (LPF) and a voltage-controlled oscillator (VCO).

In the PLL the phase or frequency of the signal fed back (feedback) the output of the VCO is compared with a reference signal input. If there is a frequency or phase difference between the two, an error signal is generated by the phase detector. This signal is filtered by the LPF into a DC control voltage that is used to control the frequency of the VCO. If the input and output signals are equal, yet the PLL operates so that they are out of phase. The phase detector produces an output voltage that is proportional to the phase difference between the input signals and output. The DC voltage output FPB VCO operates in making the VCO frequency is exactly equal to the input. If the frequency of the input signal changes, the phase detector and feel the change will produce a change in output voltage of the FPB So, of course, changes the output frequency of the VCO. The change in output frequency of the VCO is oriented such that the phase difference will be minimized. In other words, the output frequency monitor and eventually will become equal to the frequency of the input signal.
If no reference signal applied to the input of the phase detector, the output of the BPF will be zero. The VCO then generates an output signal whose frequency will be strictly a function of the VCO circuit. This is often called "free-running" (fo). Now if an input reference signal whose frequency is close to the frequency "free-running" (fo) of the VCO is applied to the input, the phase detector generates an output voltage proportional to the frequency difference. This signal is then filtered, obtaining a maintenance resulting from DC control applied to the VCO. The control voltage is such that forces the frequency of the VCO move in the direction that reduces the amplitude of the error signal. This means that the frequency of the VCO will change until it is equal to the reference frequency input. When this condition occurs, the input and output signals are synchronized or "locked" (closed). At this time, the reference input signal and the VCO output are equal in frequency but different in phase. This difference in phase between these two signals that cause the phase detector to produce an error voltage at the input of the VCO to hold the PLL "locked" in the input signal. Changing the frequency of the reference signal input, of course, will cause the output of the VCO to track the input signal is above or below its prior value.
The range of frequencies over which the PLL monitor an input signal and remains "locked" is known as the lock range. This is a band of frequencies above or below the frequency of the VCO free-running. The PLL can track and "Lockar" within any input frequency in this range.
If a reference signal input out of range of the PLL Lock is applied, the PLL simply produces output in its free-running frequency (fo). However, if the input signal is varied such that it becomes close to the free-running frequency, the PLL may capture the input signal. This means that the PLL circuit can now function properly where the phase detector may produce an error signal which forces the VCO frequency to be equal to the input frequency. When the frequency reference input become close enough to the frequency of the VCO, this effect captures rushes and a condition "Locked" eventually happens. In such conditions, the VCO output will follow the variations of the input frequency within the range of lock.
The frequency range over which a PLL can capture a signal is known as capture range. As the range of lock, it is centered on the free-running frequency. However, the capture range is usually narrower than the range of lock.
This frequency selectivity characteristic of PLL, provides the same function as bandpass filter. Because of these characteristics, the PLL is a prime regulator of signal that can eliminate noise present in an input signal as well as unwanted interference. The PLL not only provides filtering, but can also track changes in input frequency. This is one of the many applications of the PLL.
A common application is as the PLL frequency demodulator. Since the PLL can quickly monitor changes in input frequency, it is widely used in applications FM.
If a modulated carrier frequency is applied to the input, the VCO to follow, if the frequency deviation of the input signal remains within the range of lock. The VCO follows the signal because of the voltage error produced by the phase detector and the VCO FPB strength accompanies it. The output of the VCO should be identical to the FM input signal, the loop remains locked.
The VCO generates a carrier frequency that is modulated by the error signal. For this reason, the error signal must be equal to the audio signal or other information modulated at the entrance.
The output signal from the LPF is then modulating the original signal. See Figure 2 below.

Since the VCO has a linear voltage / frequency, output is not distorted representation of information originally used to modulate the carrier frequency.
The PLL is undoubtedly the best available FM demodulator. Its frequency selectivity, linearity and good signal / noise ratio is much higher than the conventional discriminator and other forms of FM detectors.
[h=2]FREQUENCY SYNTHESIZER[/h]A frequency synthesizer is a very stable signal source which can be varied over a specific frequency range, usually in defined increments or steps.
The big advantage of a PLL synthesizer is its ability to generate a wide range of frequencies with high accuracy using only a single stable reference source.
A PLL synthesizer with a simple crystal reference can quickly generate more than 100 frequencies that are as stable as a single crystal frequency reference.
Figure 3 shows the basic block diagram of a PLL synthesizer.
The primary difference between a standard and a PLL synthesizer is that a stable crystal oscillator is used in place of the reference source input. In addition, a binary frequency divider is connected in the feedback path (feedback) between the VCO output and the input of the phase detector. The frequency divider is made ​​with a digital circuit Flip-Flop or counters.
To perform a frequency change, the ratio of frequency division is made ​​variable. Changing the frequency division ratio in steps, the output frequency can be varied in discrete increments. With the division ratio of the fixed frequency, the output of the PLL remains locked, and is as stable as the reference source input. If the frequency division ratio is changed, a phase difference is detected, and thereby causes the VCO to change to a new frequency.
In a PLL synthesizer, the output frequency is a function of crystal frequency reference and frequency division ratio. Note the relationship between the frequency reference and the relationship and division of the signs of the figure below.

The reference signal is 1MHz. The VCO output frequency is 10MHz. This output is divided by 10 resulting in a frequency of 1MHz which is applied to the phase detector.
With two equal signals at the input of the phase detector, the output is locked and remain at 10MHz. Changing the division ratio for dividing by 9, will cause the VCO output signal to go 9MHz. The reason for this is simple, to the input of the phase detector see the 1MHz frequency divider, the output must follow to change or 9MHz. Thus, changing the frequency division ratio changes the output frequency. Note also that the increment of change is equal to the reference frequency input.
In the picture above we note that the output frequency is the multiple of the reference frequency. For this reason, the PLL multiplier is an excellent frequency. The multiplication factor is determined by the ratio of division.
IMPROVEMENTS IN FREQUENCY SYNTHESIZER - PLL

In the above simple technique uses a crystal oscillator to generate the input reference frequency, a VCO to produce an output signal, and a phase detector and filter to provide the correction signal to ensure "tracking". A programmable frequency counter (divider) in loop allows adjustment of output frequency to any desired multiple of the input frequency.
A complex programmable counter to work at high frequencies (> 200MHz) is very expensive. To reduce the cost of the project and for operation in VHF, for example, you can use a mixer or a prescaler. In the circuit with mixer (Fig. 5) is inserted between the VCO and divider "N" in the feedback network, a mixer that receives the frequency of the VCO and a crystal oscillator, the output frequency is equal to the difference of the two mixer input frequencies. A prescaler (fig.6), a divisor "P" fixed is also inserted into the feedback network. The two circuits have the function of reducing the frequency of the input programmable divider.

A wide range of operating frequencies can be achieved using a "Dual Modulus Prescaler" as shown in figure 7.
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Fig.7 - USING DUAL MODULUS PRESCALER
PRESCALER = Integrated Circuit For High Frequency Divider
DUAL MODULUS = Integrated Circuit PLL
FO = Output Frequency
N = Programmable Divider
The = Programmable Divider
FR = Frequency Reference
P = 64 splitter
CALCULATIONS
DT (Division Total) = (P x N Divisor Divisor) + A Divider
In practice boils down to two divisions arithmetic. For example, for the output frequency of the VCO equal to 155.370 MHz, the first division is made ​​as follows:
DT = FO (in Hz) ¸ FR (in Hz)
DT = 155370000 ¸ 10,000 = 15,537
15537 is the division's total combination of three divisors P, N and A. The second division is more simple and is made ​​as follows:
DT = (P x SPLITTER SPLITTER N) + A DIVIDER
Since P is fixed at 64, was already calculated and DT, to find the value of N so divided:
Divider N = DT ¸ Divider = P> N = 15.537 ¸ 64 = 242, ....
The result is an integer value, 242 in the example with a fractional part as appropriate and should be discarded.
The divisor A is the remainder of dividing 15,537 by 64, which is 49. This is because 242 x 64 = 15,488, then 15,537 (DT) - 15,488 = 49.
Therefore DT = (P x N) + A => DT = (64 x 242) + 49 = 15537
The above example was as follows:
FO = Output Frequency = 155.370 MHz
N Programmable Divider = 242 =
The = 49 = Programmable Divider
FR = Frequency Reference = 10 KHz
P = 64 splitter
The example that was given is based on PLL MC145152 and MC12017 Prescaler, both of which are unfortunately motorola obsolete, but are still found in trade in Sao Paulo.
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[jfrras]

اینهم یه مقاله کامل دیگه و نمونه مدارش:

[hide]

[/hide]
MC145152 PLL SYNTHESIZER WITH AND PRESCALER MC12017
I present here an excellent MC145162 PLL synthesizer with, and MC12017 Prescaler VCO using FET 2SK19. Can be used to mount the transmitters and receivers to 500MHz. The frequency of operation is scheduled through jumps. Programmers can be designed using CMOS or TTL logic, microprocessor or microcontroller to program attendance, including digital display of the frequency of operation.
DESCRIPTION OF OPERATION OF SYNTHESIZER
In figure 1 is shown a schematic diagram of the synthesizer which is formed by a PLL circuit simple. A PLL is basically an electronic servo-loop. The function of a PLL is to detect and track small differences in phase and frequency between the crystal reference (pin 26 CI1) and frequency input (pin 1 IN). It is based CI1 which is an LSI (large scale integration). The reference oscillator of 10.240 MHz on pins 26 and 27 CI1, is controlled by the crystal XTAL1 reference. The fruit of the PLL synthesizer, already divided by CI2 is applied to pin 1 of CI1. The two frequencies, pin 1 and pin 26 are again divided by the dividers internal to both reach the value of 10KHz, when its phase compared by phase detector, also internal. This value is mutual 10KHz frequency reference FR.O result of this comparison phase, phase R and phase V, leaving the pins 7 and 8 and CI1 are applied on doors, inverting (pin 2) and non-inverting (pin 3), CI3, which is a low-pass filter, which has the function of filter and amplifier loop amplifier (link). CI1 then reportedly phases of R and V, has at its output, pin 6 a DC voltage proportional to the difference between R and V, and can go from zero to +9 VDC Volt, its voltage VDD. This DC voltage polarizes the varicap diode D2 (Figure 2), determining a correction in the ability of the diode and by extension a correction in the frequency of the VCO, formed by FET 2SK19. As the voltage of pin 6 CI3, we fix the frequency of the VCO according to the programmed frequency, avoiding that it varies and keeping accurate as the frequency of the crystal XTAL1. This absolute (% accuracy) and in terms of temperature variation of +-5ppm. The modulating audio signal applied at the input terminal, operates in voltage D1, promoting algebraic sums instant in the same dc voltage and with it, the ability to instantly changing D1, causing instant variations of the VCO frequency, which in reality is a real frequency deviation, which in this case, broadcast FM, is a maximum +-75KHz. D2, C4, L1 and CT1 form the tank circuit of the voltage controlled oscillator.
The VCO signal is delivered to Q2, which is an insulator (Buffer), which isolates the VCO from the influences of the following circuits. The signal picked up at the collector of Q2 is sent to the splitter (Prescaler) CI2, which directs the signal to return to the LSI, forming the link phase tied (PLL - Fhase Locked Loop). CI2 is a splitter-type digital ECL (emitting coupled logic) whose logic levels "0" and "1" are respectively +3.15 and +4.05 volts. Not having to spend time to saturate or cut the current work, this splitter is capable of operating at frequencies up to 500MHz. The normal division is 64 times. But as we need divisions fractional part of the duty cycle (duty cycle) is transformed into divide-by 65 times, the PULSE SWALLOW (pulse SP inhibitor) and integrated stops counting the 65th pulse, as many times as necessary. This is done by the pin 9 CI1 Swallow that sends the pulse to pin 1 of IC2. Pin 9 removes this information from the "inner logic control," whose function, having or not having the Swallow Press, depends on the frequency you want to synthesize this information given by programming jumps connected to CI1. The frequency of the VCO is then divided by 64 or 65 by CI2 (divisor P) is applied to pin 1 CI1, where it undergoes new division, now by the divider N of 10 internal counter Bits programmed by jumps across pins N0 to N9, called divider more significant. Depending on the choice of the frequency programmed in jumps, by applying on its pin 10 bits, for example: 0110011101. The output of this divider is applied as the internal phase detector and is ready to be compared. But the signal pin 1 is also divided by the divider A 6-bit counter, also programmed by jumps through pins A0 to A5, called splitter less significant or Swallow Pulse. Putting up all input N's and A's level "0" (Zero), sums up the lowest frequency possible, and vice versa, with level 1, the highest frequency possible within the system included in the LSI. With N9 (pin 20) grounded, are synthesized within the VHF frequencies; N9 with "1", sums up frequencies above 250MHz. Therefore N9 will always be grounded to the frequencies range from 88 to 108 MHz When any programming pin stay open, will be with logical level "1" due resistors (Pullup Resistor) internal to LSI. Then, with the pre-divider and CI2 with internal dividers LSI (CI1), down the VCO frequency synthesized by VHF to 10KHz, the required phase comparison made ​​by the detector's internal LSI. So whatever frequency synthesized by the VCO, it forces us to lower it always to 10KHz, this division achieved initially by CI2 commanded by Swallow and Pulse primarily by internal dividers N and A, programmed by jumps through 13 bits.
With the return signal to the phase detector, the loop completed (ELO) as the signals R and V "born" at the detector, which are products of comparison signal of the VCO, pin 1, with the signal from the reference oscillator Crystal XTAL1, pins 26 and 27. Note that both signals must be divided to 10KHz, which is the real value of the reference frequency RF.
The mooring link (locking loop) is essential for precise and controlled synthesis of any frequency. If the loop to lose lock (Lock Less), an alarm signal is generated by the phase detector, the detector exciting mooring (Lock Detect) pin 28 and putting in a train of digital pulses of the order of 9KHz, which saturate Q1, making light the LED D1, indicating that, or that the frequency is outside the programmed setting or VCO's fault loop.
The oscillation frequency of the crystal XTAL1, developed on pins 26 and 27 CI1, is applied to the divider 12-bit R counter and after applied to the phase detector, since the frequency of 10KHz. This divider is fed with 12 bits programmed by four pins (RA0), 5 (RA1) and 6 (RA2) through which these pins program a ROM (read only memory) internal to the actual LSI. This memory is powered by one of three binary decoder input lines and eight output, whose inputs are the three pins 4, 5 and 6. So to program the frequency division already known of a crystal, simply apply or not, ground levels on pins RA0, RA1 and RA2. Applying a "jump" to the land, it is guaranteed level "0" (zero) in the input grounded. Leaving it free, without anything, the LSI internal Pullup Resistor, transmits level "1" to automatically input and the same reads "1" obviously. Since we have three entries this gives 8 possibilities to program the divider and could have up to 7 other frequencies to be divided. Just below the explanation of how we calculate the frequency reference.
In the VCO and through C17, is removed from the RF signal for application to external circuits such as transmitters and receivers. Attention! It should be an insulator fitted (Buffer), which isolate the VCO from the influences of the following circuits.
CI3 may be replaced by LM741.
For the more skilled, L1 can be printed on the printed circuit board itself.
FIGURE 1 - PLL - To copy the picture, click with the right mouse button on the image and select "save picture as" or see, simply click on the picture.

FIGURE 2 - VCO

CALCULATIONS AND PROGRAMMING OF DIVIDERS
We begin by dividing the frequency of reference.
* Note that in the table below the logic "0" pin is grounded, and logical level "1", the pin is open.

PIN 6 RA2	PIN 5 RA1	PIN 4 RA0	VALUE DIVISION
0	0	0	8
0	0	1	64
0	1	0	128
0	1	1	256
1	0	0	512
1	0	1	In 1024
1	1	0	In 1160
1	1	1	In 2048

* 01) - Let's calculate the frequency of the crystal more appropriate or suitable.
Ex: Multiplying table for 1024 10.000Hz (frequency reference) = 10,240,000 or 10.240 MHz => This is the value of the crystal used in our project, due to be more common in the market. Program jumps as the table above.
FR = Freq. Crystal Reference ÷ 1024 = 10KHz
FR = Frequency of reference
FC = Frequency of Crystal Reference
FC = FR x 1024 => 1024 = 10,000 x = 10.240 MHz 10.240.000KHz
FC = 10.240 MHz
* 02) - Now let's calculate the values ​​of divisors "N" and "A" of the PLL (CI1).
FS = Output Frequency
N = Programmable Divider
The = Programmable Divider
FR = Frequency Reference
P Divisor = 64 - PRESCALER
DT (Division Total) = (P x Divisor Divisor N) + A Divider
In practice boils down to two divisions arithmetic. For example, for the output frequency of the VCO equal to 100.1 MHz, the first division is made ​​as follows:
DT = FS (in Hz) ÷ FR (in Hz)
DT = 100100000 ÷ 10000 1 = 0010
1 0010 is the division's total combination of three divisors P, N and A. The second division is more simple and is made ​​as follows:
DT = (P x SPLITTER SPLITTER N) + A DIVIDER
Since P is fixed at 64, was already calculated and DT, to find the value of N so divided:
DIVIDER ÷ N = DT DIVIDER = P> N = 10,010 ÷ 64 = 156, ....
The result is an integer value, 156 in the example with a fractional part as appropriate and should be discarded.
The divisor is the rest of the division 1 0010 by 64, which is 26. This is because 156 x 64 = 9984, then 10010 (DT) - 9984 = 26.
Therefore DT = (P x N) + A => DT = (64 x 156) + 26 = 10010
The above example was as follows:
FS = Output Frequency = 100.100 MHz
N Programmable Divider = 156 =
The = 26 = Programmable Divider
FR = Frequency Reference = 10 KHz
P Divisor = 64 - PRESCALER
See details on the PLL blocks in the PLL Learn How It Works
* 03) - With the values ​​of divisors "N" and "A", we will see how to program the jumps.
The values ​​found for N = 156 and A = 26 are decimal, so we have to convert them to binary as follows:
With the conversion table value 156.

DIVISIONS SUCCESSIVEVALUES IN DECIMAL	DEBRISTORQUE VALUES IN
156 0 78	0 = N0
78 0 39	N1 = 0
39 1 19	1 = N2
19 1 9	1 = N3
9 1 4	1 = N4
4 2 0	N5 = 0
2 0 1	N6 = 0
1 1 0	N7 = 1
---	* N8 = 0
---	* N9 = 0

In the table have values ​​N0 to N9. Recalling that logic level "0", the pin of the IC should be grounded, and logical level "1", the pin should be left open.
* N8 and N9 had no rest, but still must be grounded.
Table with the conversion value of 26

DIVISIONS SUCCESSIVEVALUES IN DECIMAL	DEBRISTORQUE VALUES IN
26 0 13	0 = A0
13 1 6	1 = A1
6 0 3	A2 = 0
3 1 1	A3 = 1
1 1 0	1 = A4
---	* A5 = 0

In the table we have the values ​​of A0 to A5. Recalling that logic level "0", the pin of the IC should be grounded, and logical level "1", the pin should be left open.
* A5 had no rest, but still must be grounded.

​

 

[fromgautam]

Hello all,
I am a HAM Radio Operator and have VHF SET using Motorola MC145152 PLL chip
I want to control the MC145152 DATA and Address pin using pic IC so that it may be controlled using two switches and displayed on 16X2 LCD.
Kindly help me.
Your's
Kumar Gautam

 

[همتا]

Hi Mr. Kumar please write Farsi problems more accurately express yourself to friends to help you be successful